1. Field of the Invention
The present invention relates to a complementary metal-oxide semiconductor fabricated as an integrated circuit.
2. Description of the Prior Art
The complementary metal-oxide semiconductor is widely known by the abbreviated term CMOS. The CMOS is a combination of N- and P-channel enhancement-mode devices mounted on a single silicon chip. The advantages thereof include low quiescent power dissipation and high operating speed.
In the conventional CMOS structure, a P channel device is formed in an N.sup.- layer, that is an N-substrate and an N channel device is formed in a P layer which is contained in a part of the N-substrate and is called a P-well. In a highly integrated circuit such devices are separated from one another by no more than a few microns, and a four region PNPN structure is thereby formed in the single silicon chip. This PNPN structure may function as a parasitic silicon-controlled rectifier, that is, an SCR. However, since the SCR remains turned on when external electric noise is applied thereto and maintains a latched status until the anode voltage is removed therefrom, a malfunction occurs in the CMOS or, in the worst case, the CMOS is damaged by a very large short-circuit current flowing through the parasitic SCR. This fact has already been known as the so-called latchup phenomenon.
In the prior art, firstly, a CMOS device which can eliminate the above mentioned latchup phenomenon has been proposed in U.S. Pat. No. 3,955,210. The structural feature of this prior art CMOS is represented by a guard region. Secondly, a CMOS device which can eliminate the above mentioned latchup phenomenon has also been known in the technical field to which the present invention pertains. The structural feature of this latter CMOS is represented by a first heavily doped P.sup.+ region formed in the P-well, as well as the N.sup.+ regions which act as source and drain, and a second heavily doped N.sup.+ region formed in the N-substrate, as well as the P.sup.+ regions which act as the other source and drain.
The above mentioned two kinds of prior art CMOSs are useful for eliminating the respective latchup phenomena. However, each of these CMOSs has a defect in that the CMOS becomes relatively large in size due to the presence of the above mentioned guard region or the first and second heavily doped regions. Accordingly, it is difficult to fabricate the very highly integrated circuits in the single silicon chip.